The following will describe an active matrix liquid crystal display device as an example of image display devices related to the technologies of interest in the present invention. However, the present invention is not limited to the example and is equally applicable to image display devices of other types.
One of known, conventional image display devices is a liquid crystal display device of an active matrix drive type. The liquid crystal display device as shown in FIG. 132, is composed of a pixel array ARY, a scan signal line drive circuit GD, and a data signal line drive circuit SD. The pixel array ARY includes large numbers of scan signal lines GL and data signal lines SL crossing each other. A pixel PIX is provided in each segment that is surrounded by two adjacent scan signal lines GL and two adjacent data signal lines SL, forming a matrix of pixels as a whole. The data signal line drive circuit SD samples an input video signal DAT according to a timing signal, such as a clock signal SCK, amplifies the sampled data as required, and writes the data to associated data signal lines SL. The scan signal line drive circuit GD selects the scan signal lines GL sequentially according to a timing signal, such as a clock signal GCK, and controls opening/closure of those switching elements in the pixels PIX, to write to the pixels PIX the video signal (data) written to the data signal lines SL and also to cause the data written in the pixels PIN to be held.
Each pixel PIX in FIG. 132 is composed of a field effect transistor SW which is a switching element and a pixel capacitance (composed of a liquid crystal capacitance CL and an added-as-required supplemental capacitance CS) as shown in FIG. 133. Further referring to FIG. 133, the data signal line SL is connected to one of two electrodes of the pixel capacitance through the drain and source of the transistor SW acting as a switching element; the gate of the transistor SW is connected to the scan signal line GL; and the other electrodes of the pixel capacitance is connected to a common electrode line which is shared by all the pixels. The voltage applied across the liquid crystal capacitance CL changes the transmittance or reflectance of the liquid crystal, producing a display.
Now, schemes of writing video data to data signal lines will be described. A data signal line can be driven either of two schemes: analog scheme or digital scheme. The analog scheme can be classified further into point sequential drive scheme and line sequential drive scheme. The digital scheme can be classified further depending on whether or not there is provided an amplifier.
FIG. 134 shows an example of a data signal line drive circuit employing a point sequential scheme. According to a point sequential drive scheme, as shown in FIG. 134, the input video signal DAT to the video signal lines is written to the data signal lines SL by opening/closing the analog switches AS as a sampling circuit in synchronism with output pulses N (i.e., N1, N2, . . . ) from the associated stages of the shift register composed of a plurality of latch circuits FF. According to the configuration of FIG. 134, sampling-signals S, /S are produced based on a stack pulse of output signals N from two adjacent latch circuits FF, and as a result, video signals DAT at falling (trailing edge) timings of a sampling signal are written to data signal lines SL
FIG. 135 shows another example of a data signal line drive circuit employing a point sequential scheme. In FIG. 135, the data signal line drive circuit is adapted to a color display whereby three video signals corresponding to the three primary colors (R, G, B) for display are inputted to the drive circuit and outputted to individual data signal lines SL1r, SL1g, SL1b, by identical pulse signals S1, /S1, . . . .
FIG. 136 shows an example of a data signal line drive circuit employing a line sequential scheme. According to line sequential drive scheme, as shown in FIG. 136, after the video signal DAT inputted to the video signal line is picked up by means of the opening/closing of the sampling circuits AS in synchronism with output pulses N from the associated stages of the shift register composed of a plurality of latch circuits FF, those signals for a single horizontal period are transferred simultaneously to next stages and written to the data signal lines SL via an amplifier AM.
FIG. 137 shows an example of a data signal line drive circuit employing a digital scheme with no amplifier. According to the scheme, after the digital video signal DIG inputted to the video signal line is picked up by a latch circuit LT in synchronism with output pulses N from the associated stages of the shift register composed of a plurality of latch circuits FF, those signals for a single horizontal period are transferred simultaneously to next stages, converted into analog signals by a digital-analog converter circuit DA, and written to the data signal lines SL.
FIG. 138 shows an example of a data signal line drive circuit employing a digital scheme with an amplifier. According to the scheme, after the digital video signal DIG inputted to the video signal line is picked up by a latch circuit LT in synchronism with output pulses N from the associated stages of the shift register composed of a plurality of latch circuits FF, those signals for a single horizontal period are transferred simultaneously to next stages, converted into analog signals by a digital-analog converter circuit DA, amplified by an amplifier AP, and written to the data signal lines SL.
FIG. 139 shows an example of a scan signal line drive circuit. As shown in FIG. 139, the scan signal line drive circuit outputs to the scan signal line GL as scan signals, the product (AND) signals of pulse signals sequentially transferred in synchronism with the clock signal GCK and a signal GEN specifying a pulse width. As described earlier, the scan signal is used to control the writing and holding of the video signal in the pixel.
FIG. 140 is a timing chart corresponding to the configuration in FIG. 132.
If binary displayed images such as text and graphics are to be synthesized with a multitone image before producing a display, there are needed a multitone data storage section in which multitone data is recorded, a binary data storage section in which binary image data is stored, and a synthesized data storage section in which the synthesized image data is stored, and the data synthesized by means of these sections is inputted to the data signal line drive circuit SD as image data.
Incidentally, in recent years, technologies to integrate the pixel array and drive circuit for controlling the display on a single substrate have been a focus of attention for the purposes of manufacturing smaller liquid crystal display devices with improved resolution at lower mounting costs, which is illustrated in FIG. 141. Note that in the figure, SUB represents substrate, and COM represents a common terminal. In this kind of liquid crystal display device with an integrated drive circuit, since the substrate needs to be transparent (in a case where the substrate will be a part of a currently popular liquid crystal display device of a transmission type), polycrystalline silicon thin film transistors which can be provided on a quartz or glass substrate are often used as active elements.
Incidentally, a conventional image display device includes only a single pair of a data signal line drive circuit and a scan signal line drive circuit as shown in FIG. 132.
Therefore, its video display capability is limited only to a single format. Although there are some image display devices with display capabilities in more than one format, they simply convert signals (control and video signals) inputted to the display device using an external circuit; they do not differ much in structure. In other words, whichever format is used for the video display, the same circuits (the data signal line drive circuit and the scan signal line drive circuit) operate, and their power consumption hardly varies.
Incidentally, in recent years, demand is growing for display devices with reduced power consumption in response to the demand for portable apparatuses with longer battery life. The portable apparatus is not always operating; in contrary, most of the time it is standing by. Moreover, the video to be displayed and format differ during use and during standby: for example, when it is standing by, it only needs to display a menu screen and time and often does not require a fine display or a great number of display colors. Rather, reduced power consumption and resultant longer battery life are important. By contrast, when the portable apparatus is being used, it often needs to display large amounts of text and images, such as graphics and photographs, in high quality. Under these circumstances, the display module consumes relatively little power, because power consumption increases in the other parts of the portable apparatus (for example, the communications module, the input interface section, and the processing section) Demand for lower power consumption during use is therefore not so strong as during standby.
Further, in a conventional configuration where there are provided only a pair of drive circuits, such as the data signal line drive circuit and the scan signal line drive circuit, corresponding only to a single display video format, if the image display device is to display a superimposed image from a plurality of sets of image data, the data for the superimposed image needs to be synthesized prior to the input to the image display device. The synthesis process requires an external image processing circuit to be provided to synthesize a plurality of images.